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da9090b.001 january 14, 1998 1 mas9090b low voltage 14-bit linear codec 14-bit linear analog to digital and digital to analog converters 8-bit a-law or m -law companded analog to digital and digital to analog converters description the mas9090 is a high performance low power pcm codec and filter device tailored to implement the audio front-end functions required by the low voltage/low power consumption digital terminals. features applications single 2.7-3.6 v or 4.5-5.5 v supply selectable -30 c to 85 c temperature operation range 11 mw operating power (typ. at 2.7v) 15 mw operating power (typ. at 3.0v) 27 mw operating power (typ. at 3.6v) 38 mw operating power (typ. at 5.0v) digital bandpass filters 0.5 db absolute gain accuracy (untrimmed) 28-pin so and 44-pin tqfp packages pin compatible with st5090 and st5092 gsm digital cellular telephones battery operated audio front-ends for dsps isdn terminals ct2 and dect digital cordless telephones block diagram compressor tx register bandpass filter mux mux expander rx register bandpass filter ring/tone/dtmf generator + buzzer control serial control interface preamp tx gain sidetone gain tone gain buffer amplifiers clock generator mic3- mic2- mic1- mic3+ mic2+ mic1+ bz sp1- sp1+ sp2+ sp2- tx rx mclk fs co ci cs cclk lo rx gain (sp1/sp2) 1 3 2 4 en en pcm d to a converter 3 + + + -12.5...-27.5 db 1 db step si rte 0...-30 db 2 db step se oe1 oe2 te vs pcm a to d converter 1 de 0...-27 db 3 db step 0...22.5 db 1.5 db step be
da9090b.001 january 14, 1998 2 pin configuration vcca vccp nc nc sp1- sp1+ sp2- sp2+ gndp rx 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 cclk cs ci bz vcc co tx gnd fs mclk lo mic2- mic2+ mic1- mic1+ gnda mic3- mic3+ so28 n c n c n c nc nc n c n c n c nc nc nc nc nc n c n c sp1- sp1 sp2- sp2 gndp rx 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 c c l k c s c i b z v c c c o t x g n d fs mclk lo mic2- mic2+ mic1- m i c 1 + g n d a m i c 3 - m i c 3 + nc nc nc v c c a v c c p tqfp44 pin description pin name pin number type function so28 tqfp44 1,4 1,4,7,9 11,12,13 22,23,27 28,29,32 35,39,40, 43,44 no connection. vcca 2 41 p positive power supply input for analog section. vccp 3 42 p positive power supply input for speaker amplifiers. sp1- 5 2 ao speaker 1 amplifier negative output. sp1+ 6 3 ao speaker 1 amplifier positive output. sp2- 7 5 ao speaker 2 amplifier negative output. sp2+ 8 6 ao speaker 2 amplifier positive output. gndp 9 8 g speaker amplifier. rx 10 10 di receive data input. cclk 11 14 di control clock input. shifts serially into ci and co when cs is low. cclk is asynchronous with other system clocks. cs 12 15 di chip select input. ci 13 16 di control data input. bz 14 17 ao buzzer driver output. vcc 15 18 p positive power supply input for the digital section. vcca, vccp and vcc must be connected together. co 16 19 do control data output. tx 17 20 do transmit data output. data is shifted out on this during the assigned transmit slots. otherwise, tx is on high impedance state. gnd 18 21 g ground for the digital section. fs 19 24 di frame sync input. this 8khz signal defines the start of the tx and rx frames.
da9090b.001 january 14, 1998 3 pin description pin name pin number type function mclk 20 25 di master clock input. must be 512, 1536, 2048 or 2560 khz lo 21 26 do value of bit do of cr1. mic2- 22 30 ai negative differential input for mic2. mic2+ 23 31 ai positive differential input for mic2. mic1- 24 33 ai negative differential input for mic1. mic1+ 25 34 ai positive differential input for mic1. gnda 26 36 g gnda analog ground. mic3- 27 37 ai negative differential input for mic3. mic3+ 28 38 ai positive differential input for mic3. absolute maximum ratings parameter symbol conditions min max unit supply voltage v cc 7.0 v voltage at mic v cc < 5.5v -1 v cc +1 v current at any digital output 50 ma voltage at any digital input v cc < 5.5v -1 v cc +1 v storage temperature t s -55 +125 c recommended operation conditions parameter symbol conditions min typ max unit supply voltage v cc 3.0v mode (sv=0) 2.7 3.0 3.6 v 5.0v mode (sv=1) 4.5 5.0 5.5 v operating temperature t a -30 +85 c ac, testing input, output waveform input/output 0.8 vcc 0.2 vcc 0.7 vcc 0.3 vcc test points ac testing: inputs are driven at 0.8vcc for a logic '1' and 0.2vcc for a logic '0'. timing measurements are made at 0.7vcc for a '1' and 0.3 vcc for a '0'.
da9090b.001 january 14, 1998 4 electrical characteristics u digital inputs/outputs (v cc = 2.7-3.6v or 4.5-5.5v, t a = -30 c to +85 c, unless otherwise specified) parameter symbol conditions min typ max unit input low voltage vil all digital inputs dc all digital inputs ac 0.3v cc 0.2v cc v input high voltage vih all digital inputs dc all digital inputs ac 0.7v cc 0.8v cc v output low voltage vol all digital outputs, il = 10 m a all digital outputs, il = 2ma 0.1 0.4 v output high voltage voh all digital outputs, il = 10 m a all digital outputs, il = 2ma v cc -0.1 v cc -0.4 v input low current iil any digital input, gnd < v in < v il -10 10 m a input high current iih any digital input, v ih < v in < v cc -10 10 m a output current in high impedance ioz tx and co -10 10 m a u analog inputs/outputs (v cc = 2.7-3.6v or 4.5-5.5v, t a = -30 c to +85 c, unless otherwise specified) parameter symbol conditions min typ max unit input leakage i mic gnd < v mic < v cc (active mic) -100 20 +100 m a input resistance r mic gnd < v mic < v cc 50 k w load resistance r lsp1 sp1+ to sp1- 30 w load capacitance c lsp1 sp1+ to sp1- 50 nf output resistance r osp1 steady zero pcm code applied to rx, i = 1ma 1.0 w differential offset voltage from sp1+ to sp1- v osp1 alternating zero pcm code applied to rx, r l = 30 ohms -100 0 +100 mv load resistance r lsp2 sp2+ to sp2- 30 w load capacitance c lsp2 sp2+ to sp2- 50 nf input resistance r mic gnd < v mic < v cc 50 k w output resistance r osp2 steady zero pcm code applied to rx, i = 1ma 1.0 w differential offset voltage from sp2+ to sp2- v osp2 alternating zero pcm code applied to rx, r l = 30 ohms -100 0 +100 mv u power dissipation (v cc = 2.7-3.6v or 4.5-5.5v, t a = -30 c to +85 c, unless otherwise specified) parameter symbol conditions min typ max unit power down current at 3.0v i cc0 cclk, ci = 0.1v cs = vcc - 0.1v 0.08 10 m a power down current at 5v i cc0 cclk, ci = 0.1v cs = vcc - 0.1v 0.08 10 m a power up current at 2.7v i cc1 sp1 and sp2 not loaded 4 6 ma power up current at 3.0v i cc1 sp1 and sp2 not loaded 5 8 ma power up current at 3.6v i cc1 sp1 and sp2 not loaded 7.5 12 ma power up current at 5v i cc1 sp1 and sp2 not loaded 7.5 20 ma sp1 short circuit current i short 130 ma
da9090b.001 january 14, 1998 5 timing specifications u master clock timing parameter symbol conditions min typ max unit frequency of mclk f mclk programmable 512 1536 2048 khz period of mclk high/low f mck = 512 t whm t wlm measured from v ih to v ih 878 1074 ns period of mclk high f mck = 1536, 2048 t whm measured from v ih to v ih 80 ns period of mclk low f mck = 1536, 2048 t wlm measured from v il to v il 80 ns rise time of mclk t rm measured from v il to v ih 30 ns fall time of mclk t fm measured from v ih to v il 30 ns u pcm interface timing parameter symbol conditions min typ max unit hold time, mclk low to fs low t hmlf 17 ns setup time, fs high to mclk low t sfml 30 ns delay time, mclk high to valid tx data t dmht load = 100pf 100 ns delay time, mclk low to tx disabled t dmlz 10 100 ns delay time, fs high to valid tx data t dft load = 100pf non-delayed mode only 100 ns setup time, rx data valid to mclk low t srml 20 ns hold time, mclk low to invalid rx data t hmlr 10 ns hold time, mclk high to fs low t hmhf 30 ns setup time, fs high to mclk high t sfmh 30 ns delay time, mclk low to valid tx data t dmlt load = 100pf 100 ns delay time, mclk high to tx disabled t dmhz 10 100 ns hold time, mclk high to invalid rx data t hmhr 20 ns u non-delayed data timing diagram 1 2 3 45 67 8/16 12 3 4 5 6 7 8/16 12 3 4 5 6 7 8/16 t srml t hmlr t whm t wlm t dmlz t rm t fm t hmlf t sfml t dft t dmht mclk fs tx rx in companded mode the timing is applied to 8 bits instead of 16 bits.
da9090b.001 january 14, 1998 6 timing specifications u delayed data timing diagram 1 2 3 45 67 8/16 12 3 4 5 6 7 8/16 12 3 4 5 6 7 8/16 t srml t hmlr t whm t wlm t dmlz t rm t fm t hmlf t sfml t dmht mclk fs tx rx in companded mode the timing is applied to 8 bits instead of 16 bits. u non-delayed reverse data timing diagram 1 2 3 45 6 7 8/16 12 3 4 5 6 7 8/16 12 3 4 5 6 7 8/16 t srml t hmlr t whm t wlm t dmhz t rm t fm t hmhf t sfmh t dmlt mclk fs tx rx t dft in companded mode the timing is applied to 8 bits instead of 16 bits.
da9090b.001 january 14, 1998 7 timing specifications u serial control port timing parameter symbol conditions min typ max unit frequency of cclk f cclk 2.048 mhz period of cclk high t whc measured from v ih to v ih 160 ns period of cclk low t wlc measured from v il to v il 160 ns rise time of cclk t rc measured from v il to v ih 50 ns fall time of cclk t fc measured from v ih to v il 50 ns hold time, cclk high to cs low t hchs 10 ns setup time, cs low to cclk high t sslch 50 ns setup time, valid ci data to cclk high t sdch 50 ns hold time, cclk high to invalid ci data t hchd 50 ns delay time, cclk low to valid co data t dcld load = 100 pf 80 ns delay time, cs low to valid co data t dsd 50 ns delay time, cs high or 8 th cclk low to co high impedance t dsz 10 80 ns hold time, 8 th cclk high to cs high t h8chs 100 ns setup time, cs high to cclk high t sshch 100 ns u serial control port timing diagram (microwire mode) cclk cs ci co 1 2 3 4 5 67 8 1 2 3 4 5 67 8 76543 21 0 76543 21 0 76543 21 0 t whc t wlc t rc t fc t sslch t hchs t sdch t hchd t hchsh t sslch t sshch t hchs t dsd t dcld t dsz t hchsh byte 2 byte 1
da9090b.001 january 14, 1998 8 transmission characteristics u absolute levels at mic1/mic2/mic3 (v cc = 2.7-3.6v or 4.5-5.5v, t a = -30 c to +85 c, unless otherwise specified) parameter conditions min typ max unit 0 dbm0 level transmit amps connected for 20 db gain 49.26 mv rms overload level 70.71 mv rms 0 dbm0 level transmit amps connected for 42.5 db gain 3.694 mv rms overload level 5.302 mv rms u absolute levels at sp1 / sp2 (differentially measured) (v cc = 2.7-3.6v or 4.5-5.5v, t a = -30 c to +85 c, unless otherwise specified) parameter conditions min typ max unit 0 dbm0 level receive gains = 0 db 1.965 v rms 0 dbm0 level receive gains = -30 db 61.85 mv rms u transmit path amplitude response (v cc = 2.7-3.6v or 4.5-5.5v, t a = -30 c to +85 c, unless otherwise specified) parameter symbol conditions min typ max unit transmit gain absolute accuracy, hpt = 0 hpt = 1 g xa tx gain set to maximum, measure deviation of digital pcm code from ideal 0 dbm0 pcm code at tx -0.5 -0.4 0 0.1 0.5 0.6 db transmit gain variation with programmed gain g xag measure tx gain over the range (from max to min). calculate the deviation from the programmed gain relative to g xa , i.e. g xag = g actual - g pro g - g xa -0.5 0.5 db transmit gain variation with temperature g xat measured relative to g xa min. gain < g x < max. gain -0.1 0.1 db transmit gain variation with supply g xav measured relative to g xa g x = maximum gain -0.1 0.1 db transmit gain variation with frequency g xaf relative to 1.015625 khz, multitone test technique used min. gain < g x < max. gain hpt=0 f = 60 hz -34 -33 db f = 100 hz -36 -35 f = 200 hz -11 -10 f = 300 hz -1.5 -0.7 0.5 f = 400 hz to 3000 hz -0.5 0.5 f = 3400 hz -1.5 -1.3 0.0 f = 4000 hz -17 -16 f = 4600 hz -62 -61 f = 8000 hz -68 -67 hpt=1 f = 60 hz to 3000 hz f = 3000 to 8000 hz, see hpt=0 -0.5 0.5 db transmit gain variation with signal level g xal sinusoidal test method reference level = -10 dbm0 v mic = -40 dbm0 to +3.0 dbm0 -0.5 0.5 db v mic = -50 dbm0 to -40 dbm0 -0.5 0.5 v mic = -55 dbm0 to -50 dbm0 -1.2 1.2 tone generator gain absolute accuracy g xtone measure deviation of digital pcm code from ideal 0dbm0 pcm code at tx -0.3 0.6 db
da9090b.001 january 14, 1998 9 transmission characteristics u receive path amplitude response (v cc = 2.7-3.6v or 4.5-5.5v, t a = -30 c to +85 c, unless otherwise specified) parameter symbol conditions min typ max unit receive gain absolute accuracy, hpx = 0 hpx = 1 g ra1 rx gain programmed to maximum, apply -6dbm0 pcm code to rx, measure sp1+ to sp1- -0.5 -0.4 0 0.1 0.5 0.6 db receive gain absolute accuracy, hpx = 0 hpx = 0 g ra2 rx gain programmed to maximum, apply -6dbm0 pcm code to rx, measure sp2+ to sp2- -0.5 -0.4 0 0.1 0.5 0.6 db receive gain variation with programmed gain g rag1 measure sp1 gain over the range from maximum to minimum setting, calculate the deviation from the programmed gain relative to g ra1 , i.e. g rag1 = g actual -g pro g - g ra1 -0.5 0.5 db receive gain variation with programmed gain g rag2 measure sp2 gain over the range from maximum to minimum setting, calculate the deviation from the programmed gain relative to g ra2 , i.e. g rag2 = g actual -g pro g - g ra2 -0.5 0.5 db receive gain variation with temperature g rat measured relative to g ra1 or g ra2 min. gain < g r < max. gain -0.1 0.1 db receive gain variation with supply g rav measured relative to g ra1 or g ra2 g r = maximum gain -0.1 0.1 db receive gain variation with frequency (sp1 and sp2) g raf relative to 1.015625 khz, multitone test technique used. min. gain < g r < max. gain. hpr = 0 f = 60 hz -34 -33 db f = 100 hz -38 -35 f = 200 hz -12 -10 f = 300 hz -1.5 -0.5 0.5 f = 400 hz to 3000 hz -0.5 0.5 f = 3400 hz -1.5 -1.3 0.0 f = 4000 hz -15 -14 hpr = 1 f = 60 hz to 3000 hz -0.5 0.5 f = 3000 to 4000 hz, see hpr=0 receive gain variation with signal level (sp1) g ral1 sinusoidal test method, reference level = -10 dbm0 rx = -40 dbm0 to -3 dbm0 -0.5 0.5 db rx = -50 dbm0 to -40 dbm0 -0.5 0.5 rx = -55 dbm0 to -50 dbm0 -1.2 1.2 receive gain variation with signal level (sp2) g ral2 sinusoidal test method, reference level = -10 dbm0 rx = -40 dbm0 to -3 dbm0 -0.5 0.5 db rx = -50 dbm0 to -40 dbm0 -0.5 0.5 rx = -55 dbm0 to -50 dbm0 -1.2 1.2 tone generator gain absolute accuracy g rtone measure signal level at sp1 -1 1 db
da9090b.001 january 14, 1998 10 transmission characteristics u envelope delay distortion with frequency (v cc = 2.7-3.6v or 4.5-5.5v, t a = -30 c to +85 c, unless otherwise specified) parameter symbol conditions min typ max unit tx delay, absolute d txa f = 1600 hz 800 m s tx delay, relative d txr f = 500 - 600 hz 15 m s f = 600 - 800 hz 20 f = 800 - 1000 hz 5 f = 1000 - 1600 hz -15 f = 1600 - 2600 hz -40 f = 2600 - 2800 hz -50 f = 2800 - 3000 hz -50 rx delay, absolute d rxa f = 1600 hz 800 m s rx delay, relative d rxr f = 500 - 600 hz 15 m s f = 600 - 800 hz 20 f = 800 - 1000 hz 5 f = 1000 - 1600 hz -15 f = 1600 - 2600 hz -40 f = 2600 - 2800 hz -50 f = 2800 - 3000 hz -50 u noise (v cc = 2.7-3.6v or 4.5-5.5v, t a = -30 c to +85 c, unless otherwise specified) parameter symbol conditions min typ max unit tx noise, p weighted n txp v mic = 0v, de = 0, tx gain set to 15 db -72* -68* dbm0 rx noise, a weighted (max. gain) n rxa receive pcm code = positive zero si = 0, rte = 0 140* 190* m v rms noise, single frequency n s mic = 0v, loop around measurement from f = 0 hz to 100 khz -76 -50 dbm0 psrr, tx ppsr tx mic = 0v v cc = 3.3v dc + 50 mv rms f = 0 hz to 50 khz 30 44 db psrr, rx ppsr rx pcm code equals positive zero v cc = 3.3 v dc + 50 mv rms f = 0 hz to 4 khz 30 54 db f = 4 khz to 50 khz 30 spurious out-band signal at the output (relative to signal) s os rx input set to -6 dbm0 pcm code, 300 hz 3400 hz input pcm code applied at rx 4600 hz - 5600 hz -45 db 5600 hz - 7600 hz -45 7600 hz - 8400 hz -50 8400 hz - 20000 hz -50 common mode rejection ratio cmrr x mic = -6dbm0, max. gain -74 -45 db tone generator noise n tone dtmf frequencies, tx/sp output -36 -28 dbm0 *limit is used to speed up automatic testing. true value is less.
da9090b.001 january 14, 1998 11 transmission characteristics u distortion (v cc = 2.7-3.6v or 4.5-5.5v, t a = -30 c to +85 c, unless otherwise specified) parameter symbol conditions min typ max unit signal to total distortion tx (up to 35 db gain) s tdtx sinusoidal test method (linear 300 hz to 3400 hz weighting). typical values measured level = 0 dbm0 56 64 db with 35 db gain level = -6 dbm0 50 60 level = -10 dbm0 48 57 level = -20 dbm0 43 53 level = -30 dbm0 38 44 level = -45 dbm0 24 29 level = -55 dbm0 15 19 single frequency distortion transmit s dtx 0 dbm0 input signal -70 -56 db signal to total distortion sp1/sp2 (up to 20 db attenuation) s tdsp1 s tdsp2 sinusoidal test method (linear 300 hz to 3400 hz weighting). load is 1000 or 30 w . level = -6 dbm0 45* 50 60 db level = -10 dbm0 45* 48 60 level = -20 dbm0 43* 43 55 level = -30 dbm0 38* 38 50 level = -45 dbm0 24* 24 40 level = -55 dbm0 15* 15 28 single frequency distortion receive sp1/sp2 s dsp1 s dsp2 -6 dbm0 input signal -62 -45 db signal to distortion of tone generator signals s tone dtmf frequencies linear 300 hz to 3400 hz weighting. 28 42 db intermodulation imd loop around measurement voltage at mic = -10 dbm0 to - 27 dbm0, 2 frequencies in the range 300 hz to 3400 hz -61 -46 db *max. load (30 w ) and min. v cc (2.7v) u crosstalk (v cc = 2.7-3.6v or 4.5-5.5v, t a = -30 c to +85 c, unless otherwise specified) parameter symbol conditions min typ max unit transmit to receive c tx-r x transmit level = 0 dbm0 f = 300 hz to 3400 hz rx = quiet pcm code -82 -65 db receive to transmit c rx-t x receive level = -6 dbm0 f = 300 hz to 3400 hz mic = 0v -75 -60 db
da9090b.001 january 14, 1998 12 responses u rx frequency response 10 1 10 2 10 3 ?60 ?50 ?40 ?30 ?20 ?10 0 10 amplitude db frequency hz u rx frequency response (passband) 10 3 ?1.5 ?1 ?0.5 0 0.5 1 amplitude db frequency hz
da9090b.001 january 14, 1998 13 responses u rx frequency response (stopband low) 10 1 10 2 ?50 ?40 ?30 ?20 ?10 0 amplitude db frequency hz u rx frequency response (stopband high) ?60 ?50 ?40 ?30 ?20 ?10 0 amplitude db 4000 5000 6000 frequency hz
da9090b.001 january 14, 1998 14 responses u tx frequency response 10 1 10 2 10 3 10 4 ?60 ?50 ?40 ?30 ?20 ?10 0 10 amplitude db frequency hz u tx frequency response (passband) 10 3 ?1.5 ?1 ?0.5 0 0.5 1 amplitude db frequency hz
da9090b.001 january 14, 1998 15 responses u tx frequency response (stopband low) 10 1 10 2 ?50 ?40 ?30 ?20 ?10 0 amplitude db frequency hz u tx frequency response (stopband high) ?60 ?50 ?40 ?30 ?20 ?10 0 amplitude db 4000 5000 frequency hz
da9090b.001 january 14, 1998 16 functional description u operating modes when power is first applied, power-on reset circuit initializes control and data registers of mas9090 and puts it into a power-down state. during power- down state, control registers retain their initial state until they are written via the serial interface. master clock (mclk) can be inactive. the power up/down control is accomplished by changing the p-bit of the address byte of the serial interface ("0" means active and "1" power-down) or by stopping the master clock. power- down power- up power-on reset p=0, active mclk and fs p=1 no mclk u control interface control information or data is written into or read- back from the internal registers of mas9090 via the serial control port. serial control port consists of control output co, control input ci, chip select cs- and control clock cclk and supports the microwire ? *) communication protocol. all control instructions, except the single byte power up/down command require two bytes of data . to shift the data into mas9090, cclk must be pulsed eight times (cs is low). data on the ci input is shifted into the serial input register on the rising edges of cclk pulses. after 8 bit address data is shifted in, the content of the shift register is decoded and may indicate that 8 bit control word will follow. control word may start immediately after the address byte or after a single cs pulse. it is not mandatory for the cs signal to return high in between the address and the data. after the second byte is shifted in, the cs signal must return to a high state. the same process takes place for reading-back status information during the next cs low state. cs will remain low for eight cclk pulses. the data is shifted out on the co output from the serial output register on the falling edges of cclk. when cs is high, the co pin is in a high impedance state, which enables co pins of other devices to be multiplexed together. u digital data interface digital data is shifted in/out from rx/tx using master clock (mclk) and frame sync (fs) signals. fs determines the beginning of frame and its duration can vary from single cycle of mclk to squarewave. three different modes between fs and the first time slot of a data frame can be used: non-delayed normal data timing, non-delayed reverse data timing and delayed data timing. these modes are set with bits dm0 and dm1 of control register cr1. in non-delayed timing modes the first time slot begins coincident with the rising edge of the fs. in delayed timing mode the fs must be active at least one half cycle of mclk before the beginning of the first time slot. bit en of control register cr1 enables the voice data transfer on tx and rx pins. data is shifted out from tx output on the rising edge of mclk and shifted into rx on falling edge of mclk on assigned time slot. in non-delayed reverse mode the data is shifted with different edge of mclk (on falling edge from tx and on rising edge into rx). tx output is in tristate condition during non selected time slots. the tx output transmits 8 bits of encoded data (a-law or m -law) or 16 bits (14 effective bits, 2 lsb bits zero) of linear data when compressor is bypassed. two time slots (b1 and b2) can be used in two formats: in format 1, time slot b1 corresponds to eight mclk cycles starting immediately after the rising edge of fs and time slot b2 starts immediately after the b1 is ended. a two-bit space is left after b2 for insertion of possible d channel data. the position of this two-bit data is changed in format 2 to the center of time slots b1 and b2. the data format is selected by bit ff in control register cr0 and time slots b1 and b2 are selected by bit ts in control register cr1. u control channel access to pcm interface when companded code is selected it is possible to access the selected time slot (b1 or b2) by writing data bytes to internal registers cr2 and cr3. the byte written to cr3 is transmitted from tx with the following frame in place of pcm data if bit mx (3) of cr1 is selected. to implement a continuous data flow from interface to b channel a control byte has to be sent on each pcm frame. the byte written into cr2 is sent through the receive audio path (rx) if bit mr (4) of cr1 is selected. cr2 can also be used to read the rx input. in order to implement a continuous data flow from b channel to the interface, register cr2 has to be read at each pcm frame. *) trade mark of national semiconductor
da9090b.001 january 14, 1998 17 functional description u tx audio path analog front end provides three identical differential inputs (mic1, mic2, mic3) for capacitive connection of microphones or auxiliary audio circuits. desired input signal is selected with bits vs and te (6 and 7) of register cr4 and forwarded to a low noise preamplifier. preamplifier has 15.7 db gain and its output is fed to the programmable gain amplifier which provides an additional gain from 0 to 22.5 db in 1.5 db steps. gain is controlled with bits 4-7 of register cr5. an active rc anti alias filter is used to prevent signal folding during the sampling. accurate analog to digital conversion is done by using a sigma-delta modulator followed by a decimation filter. digital multiplexer (bit de (0) in cr 7) is used to select the input of a digital bandpass filter (300- 3400 hz). the input can be taken from the output of the decimator or from an internal ring/tone generator. the bandpass filter output contains hard clipping saturation logic for signals exceeding overload level (+3.14 db). highpass part of the bandpass filter can be bypassed with bit hpt of register cr10. output data can be compressed by using ccitt a- law or m 255-law coding. the compression code is selected with bits cm (5), ma (4) and ia (3) of register cr0. u rx audio path received signal is transferred into rx register in 8 bit encoded format or in 16 bit linear format. the data is expanded by using a-law or m -law signal encoding according to ccitt a and m 255 laws. the expansion code is selected with bits cm (5), ma (4) and ia (3) of register cr0. signal is then passed through a bandpass filter (bandpass 300-3400 hz). the high pass section of the filter can be bypassed with bit hpr of register cr4. the input signal of rx gain3 is controlled with bits si (5), rte (2) and se (0) of register cr4. bit si activates the transmit side tone signal, bit rte activates the ring/tone generator and bit se activates the received signal to be summed to the gain input. rx gain3 can be programmed with bits 4-7 of register cr6 from 0 db to -30 db with -2db steps. it contains also hard-clipping saturation logic. after gain adjustment the signal is fed to a digital sigma-delta modulator followed by a switched capacitor (sc) reconstruction filter and a continuous time smoothing filter. filtered analog signal can be directed to a speaker amplifier (sp1) or to an extra analog output amplifier (sp2) with bits oe1 (4) and oe2 (3) of register cr4. gains can be set with register cr6 in the range of 0 to -30 db in -2 db steps. differential analog outputs (sp1, sp2) are capable of directly driving output load of 30 w with power level up to 66mw. also ceramic receivers up to 50nf can be used. power up transient noise suppression is used in both outputs. u ring and tone generator ring/tone generator is able to generate one or two sinewave or squarewave frequencies (including dtmf tones) to the transmit (tx) receive (rx) or buzzer paths. generated frequencies can be programmed with registers cr8 and cr9. one of the three frequency ranges can be selected with bits dft and hft of register cr10. output signal level of the tone generator can be selected from 0 to -27 db with -3db steps with bits 4-7 of register cr7. single ended bz output is used to drive a buzzer by using an external bipolar transistor with pulse width modulated (pwm) squarewave signal f1 (cr8). this pwm signal can also be amplitude modulated with signal f2 (cr9). maximum load for bz is 5 k w and 50pf. implementation of tone generator is fully digital. therefore no amplitude or frequency response variations (at tx output) over temperature, power supply or from unit to unit exist.
da9090b.001 january 14, 1998 18 functional description u digital interface format format 1 fs fs mclk rx tx delayed timing non-delayed timing b1 b2 b2 b1 x x x 12345678 format 2 fs fs mclk rx tx delayed timing non-delayed timing b1 b2 b2 b1 x x x 12345678
da9090b.001 january 14, 1998 19 functional description u registers register map register address byte i/o data byte 76543210 76543 2 10 power p x x x x x 0 x cr0 p 0 0 0 0 0 1 x write f1 f0 cm ma ia ff b7 dl p 0 0 0 0 1 1 x read cr1 p 0 0 0 1 0 1 x write dm1 dm0 do mr mx en ts sv p 0 0 0 1 1 1 x read cr2 p 0 0 1 0 0 1 x write input data [0:7] p 0 0 1 0 1 1 x read cr3 p 0 0 1 1 0 1 x write output data [0:7] p 0 0 1 1 1 1 x read cr4 p 0 1 0 0 0 1 x write vs te si oe1 oe2 rte hpr se p 0 1 0 0 1 1 x read cr5 p 0 1 0 1 0 1 x write tx gain [4:7] side tone gain [0:3] p 0 1 0 1 1 1 x read cr6 p 0 1 1 0 0 1 x write sp1 gain [4:7] sp2 gain [0:3] p 0 1 1 0 1 1 x read cr7 p 0 1 1 1 0 1 x write tone gain [4:7] f1 f2 sn de p 0 1 1 1 1 1 x read cr8 p 1 0 0 0 0 1 x write binary word used for calculating f1 p 1 0 0 0 1 1 x read cr9 p 1 0 0 1 0 1 x write binary word used for calculating f2 p 1 0 0 1 1 1 x read cr10 p 1 0 1 0 0 1 x write por sca hpt ext li lo dft hft p 1 0 1 0 1 1 x read cr11 p 1 0 1 1 0 1 x write be bi duty cycle for bz (0:5) p 1 0 1 1 1 1 x read cr14 x x x x x x x x for testing purposes only address byte bits: bit 0 reserved for future extensions bit 1 indicates the presence of a second byte. if cleared indicates single byte power up/down command bit 2 is write/read select bit bits 6 to 3 contain the address of register registers cr12, cr13, cr15 are not accessible msb bit (bit 7) of the address and data byte is always clocked first into or out from ci and co pins bit 7 p controls the power up/down state of the chip. p = 1 means power down data bits: all registers are cleared during power on reset or by writing to bit por of cr10 default value for all bits is zero. notice the difference between power down and por. registers can be written in both power down/up states and they retain their values in power down. both data and control registers are cleared when por bit (in cr10) is written high or during power on reset (i.e. vcc transition from 0 volts to 3-5 volts).
da9090b.001 january 14, 1998 20 functional description control register cr0 7 6 5 4 3 2 1 0 function f1 f0 cm ma ia ff b7 dl 0 0 1 1 0 1 0 1 mclk = 512 khz * mclk = 1536 khz mclk = 2048 khz not implemented 0 0 0 1 1 0 1 0 1 linear code * 2s complement * sign and magnitude 2s complement 1s complement 1 0 0 1 1 0 1 0 1 companded code m -law: ccitt d3-d4 m -law: bare coding a-law: including even bit inversions a-law: bare coding 0 1 b1 and b2 consecutive (1)* b1 and b2 separated (1) 0 1 8-bit time slot (1)* 7-bit time slot (1) 0 1 normal operation (default) * digital loop back (tx and rx muted) control register cr1 7 6 5 4 3 2 1 0 function tm1 tm0 do mr mx en ts sv 0 1 1 x 0 1 delayed data timing * non-delayed normal data timing non-delayed reverse data timing 0 1 lo latch set to 1 * lo latch set to 0 0 1 rx connected to rx path * cr2 connected to rx path (1) 0 1 tx path connected to tx * cr3 connected to tx (1) 0 1 voice data transfer disable * voice data transfer enable 0 1 b1 channel selected (1)* b2 channel selected (1) 0 1 2.7-3.6v power supply * 5.0v power supply (1) significant in companded mode only * state at power on initialization
da9090b.001 january 14, 1998 21 functional description control register cr2 7 6 5 4 3 2 1 0 function d7 d6 d5 d4 d3 d2 d1 d0 msb data sent to rx path or data received from rx input control register cr3 7 6 5 4 3 2 1 0 function d7 d6 d5 d4 d3 d2 d1 d0 msb tx data transmitted control register cr4 7 6 5 4 3 2 1 0 function vs te si oe1 oe2 rte hpr se 0 0 1 1 0 1 0 1 tx input muted * mic1 selected mic2 selected mic3 selected 0 1 internal side tone disabled * internal side tone enabled 0 0 1 1 0 1 0 1 rx output muted * sp1 output selected sp2 output selected not allowed 0 1 ring/tone to sp1 or sp2 disabled * ring/tone to sp1 or sp2 enabled 0 1 receive hp filter enabled * receive hp filter disabled 0 1 rx signal to sp1 or sp2 disabled * rx signal to sp1 or sp2 enabled control register cr5 7 6 5 4 3 2 1 0 function tx gain sidetone gain 0 0 - 1 0 0 - 1 0 0 - 1 0 1 - 1 0 db gain * 1.5 db gain in 1.5 db steps 22.5 db gain 0 0 - 1 0 0 - 1 0 0 - 1 0 1 - 1 -12.5 db gain * -13.5 db gain in 1 db steps -27.5 db gain * state at power on initialization
da9090b.001 january 14, 1998 22 functional description control register cr6 7 6 5 4 3 2 1 0 function earpiece gain (sp1) extra gain (sp2) 0 0 - 1 0 0 - 1 0 0 - 1 0 1 - 1 0 db gain * -2 db gain in -2 db steps -30 db gain 0 0 - 1 0 0 - 1 0 0 - 1 0 1 - 1 0 db gain * -2 db gain in -2 db steps -30 db gain control register cr7 76543210 function tone gain f1 f2 sn de attenuation f1 dbm0 f2 dbm0 f1+f2 dbm0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 x x 0 0 1 1 0 0 1 1 x x 0 1 0 1 0 1 0 1 0 1 0 db gain * -3 db -6 db -9 db -12 db -15 db -18 db -21 db -24 db -27 db 1.20 (2) -25.80 -0.87 (2) -27.87 -1.81 (2) -28.81 0 0 1 1 0 1 0 1 f1 and f2 muted * f2 selected f1 selected f1 and f2 in summed mode 0 1 squarewave signal selected * sinewave signal selected 0 1 normal operation * tone/ring generator connected to tx path control register cr8 76543210 function d7 d6 d5 d4 d3 d2 d1 d0 msb f1 control word control register cr9 76543210 function d7 d6 d5 d4 d3 d2 d1 d0 msb f2 control word (2) values are calculated from tx output, levels on rx are 6 db smaller x dont care * state at power on initialization
da9090b.001 january 14, 1998 23 functional description control register cr10 76543210 function por sca hpt ext l1 l0 dft hft 0 1 normal operation * set power-on-reset initialization 0 1 normal operation * scan. ci is input, dx is output. for device testing. 0 1 normal operation * bypass tx highpass filter 0 1 normal operation * read 2-bit input to the decimator. for device testing (ci and dr) 0 1 normal operation * loop from expander to compressor 0 1 normal operation * loop from tx to rx 0 0 1 1 0 1 0 1 standard frequency tone range * halved frequency tone range double frequency tone range forbidden control register cr11 7 6 5 4 3 2 1 0 function be bi bz5 bz4 bz3 bz2 bz1 bz0 0 1 buzzer output disabled (set to 0) * buzzer output enabled 0 1 duty cycle is relative to width of logic 1 * duty cycle is relative to width of logic 0 msb duty cycle control word control register cr14 ( for testing purposes only) 76543210 function am2 am1 am0 dm2 dm1 dm0 mux edx rxtest pin txtest pin 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 vsa anti-image filter dac output rx pos. reference rx neg. reference rx agnd nc nc vsa gain amplifier vsa anti-image filter vsa vsa vsa nc 0 0 0 0 1 1 0 0 1 1 x x 0 1 0 1 0 1 tx (configured for test by mux) power-on reset input of tx bandpass filter sign bit of digsdm 512 khz clock (phi1) internal frame sync output of rx gain3 0 1 normal operation connect selected test outputs to tx output 0 1 normal operation enable tx output continuously * state at power on initialization
da9090b.001 january 14, 1998 24 register description control register cr0 master clock frequency selection: external mclk frequency can be 512 khz, 1.536 mhz, 2.048 mhz or 2.56 mhz. during initialization bits f1 (7) and f0 (6) must be set to select correct value for internal clock divider. default value for external mclk is 512 khz. any other value must be selected before power up command. coding selection bit cm (5) permits selection of 14-bit linear coding or companded coding. default is linear mode. in case of companded mode (cm=1) bits ma (4) and ia (3) select either m -255 or a law coding mode and the format for both. in case of linear mode (cm=0) bits ma (4) and ia (3) select the linear data to be in 2s complement, 1s complement or sign and magnitude format. digital interface format (1) bit ff (2) selects the format for tx and rx data transfer. if ff=0 format 1 is selected and channels b1 and b2 are consecutive. ff = 1 selects format 2 where channels b1 and b2 are separated by two bits. 56+8 selection (1) if bit b7 (1) is selected mas9090 takes only seven most significant bits of the companded pcm data byte. lsb bit on rx is ignored and lsb bit on tx is in high impedance state. this allows direct connection of an external in band data generator to the digital interface. digital loopback bit dl (0) selects the digital loopback mode, where data written into rx data register (cr2) from received time slot is read-back from that register in the selected time-slot on tx. no pcm decoding or encoding takes place in this mode. control register cr1 digital interface timing bit tm1 (7) selects the timing mode for digital interface. as a default (tm1=0) delayed timing mode is selected. in delayed mode (tm1=1) bit tm0 (6) selects the normal (tm0=0) or reversed timing mode (tm0=1). latch output control bit do (5) controls directly the lo output pin. bit written to do is seen inverted from the output lo. microwire access on rx path (1) when bit mr (4) is set high the data written into register cr2 is decoded each frame and sent to receive path. data input rx is ignored when mr is high. in other direction, current pcm data input received at rx can be read from register cr2 each frame. microwire access on tx path (1) bit mx (3) enables the access of write only register cr3 to tx output. when mx is set active data written to cr3 is send to tx output every frame. pcm encoder is ignored. transmit/receive enable/disable bit en (2) enables or disables voice data transfer on tx and rx pins. when disabled pcm data from rx input is not decoded and tx output is on high impedance state. default value is disabled. b-channel selection (1) bit ts (1) selects the active channel b1 or b2. default (ts=0) is b1 channel. (see fig on page 14) power supply selection bit sv (0) selects the main supply voltage used. when sv is low a 2.7-3.6 v supply is assumed. when sv is high 4.5-5.5 v is expected. control register cr2 (1) data sent to receive path or data received from rx input is seen in register cr2. see register cr1 bit mr (4). control register cr3 (1) tx data transmitted. refer to bit mx (3) in cr1. (1) significant in companded mode only
da9090b.001 january 14, 1998 25 register description control register cr4 transmit input selection bits vs (7) and te (6) select active input (mic1, mic2 or mic3). default is that all inputs are muted. transmit (tx) gain can be adjusted from 0 to 22.5 db in 1.5 db steps with register cr5 bits (7:4). sidetone selection transmit signal after bandpass filter can be fed back to the receive amplifiers when bit si (5) is set high. output driver selection bits oe1 (4) and oe2 (3) select the active output of the rx gain to be sp1 or sp2. both outputs can be muted. ring/tone signal selection bit rte (2) connects the on-chip ring/tone generator to the rx gain input. receive high pass filter selection bit hpr (1) provides possibility to bypass high pass section of the receive bandpass filter. pcm receive data selection bit se (0) enables the connection of the received signal to the rx gain input. control register cr5 transmit gain selection tx gain can be programmed from 0 to 22.5 db in 1.5 db steps with bits (7:4). sidetone attenuation selection transmit signal picked after digital bandpass filters can be fed back to rx gain. attenuation of the sidetone signal can be programmed from C12.5 db to C27.5 db in 1 db steps with bits (7:4). attenuation is relative to the input signal level of bandpass filter. control register cr6 speaker 1 and 2 gain selection the attenuation of both speaker gains can be programmed separately from 0 to C30 db in 2 db steps with bits (7:4) and (3:0). 0 dbm0 voltage at the output of the rx gain on pins sp1/2+ and sp1/2- is 1.965 vrms when 0 db gain is selected. when C30 db gain is selected the 0 dbm0 level is 61.85 mvrms. control register cr7 tone/ring gain selection output of tone/ring generator can be attenuated from 0 to C27 db in 3 db steps with bits (7:4). frequency mode selection bits f1 (3) and f2 (2) permit selection of f1 and/or f2 frequency generators. when f1 (f2) is selected the output of the tone generator is signal at the frequency programmed by the register cr8 (cr9). if both f1 and f2 are selected the output is a sum of both signals. in case of squarewave the f1 is amplitude modulated by f2. in order to meet dtmf specifications the level of f2 is attenuated by 2 db relative to f1. waveform selection bit sn (1) selects the output waveform of the tone generator to be square (sn=0) or sinewave (sn=1). dtmf selection bit de (0) permits the connection of the tone generator to the transmit path. speaker output can also be provided by using sidetone circuit (bit si of cr4) or directly connecting the tone generator to rx gain with bit rte of cr4.
da9090b.001 january 14, 1998 26 register description control registers cr8 and cr9 the frequency of both frequency generators is programmed by cr8 and cr9. when standard frequency range is selected (cr10: dft=0, hft=0) the frequency is defined by formulas: f1 = cr8 / 0.128 hz and f2 = cr9 / 0.128 hz, where cr8 and cr9 are decimal equivalents of the register content. thus any frequency between 7.8 hz and 1992 hz in 7.8 hz step can be selected. when halved frequency range is selected (cr10:dft=0, hft=1) the frequency is defined by formulas: f1 = cr8 / 0.256 hz and f2 = cr9 / 0.256 hz. thus any frequency between 3.9 hz and 996 hz in 3.9 hz step can be selected. when doubled frequency range is selected (cr10:dft=1, hft=0) the frequency is defined by formulas: f1 = cr8 / 0.064 hz and f2 = cr9 / 0.064 hz. thus any frequency between 15.6 hz and 3984 hz in 15.6 hz step can be selected. control register cr10 writing bit por (7) high puts the mas9090 in power-on-reset state and all data and control registers are cleared (including the por bit). logic low written to bit sca (6) sets the chip to scan mode. during scan ci is the input and tx is the output. used only for device testing. high written to bit hpt (5) bypasses the highpass part of the tx bandpass filter. when bit ext (4) is set active the two bit output of the adc is disabled and data is fed from pins cr and dr. used only for device testing. with bit l0 (3) it is possible to loop internally from tx to rx. bit l1 (2) permits looping from the expander output to the compressor input. frequency range selection bits dft (1) and hft (0) define the frequency range of the tone generator output. three modes are possible: halved, standard and doubled with output frequencies from 3.9996 hz and 7.81992 hz, 15.63984 hz respectively. control register cr11 when bit be (7) is high it permits the connection of f1 squarewave pulse width modulated (pwm) ring signal to buzzer driver output pin bz. signal can be amplitude modulated (am) with squarewave signal f2. when bit be is low (buzzer disabled) the state of the output pin bz is logical inversion of bit bi (6). this works also in power-down state. when buzzer output is enabled (be = 1) bit bi (6) controls the polarity of the duty cycle selection. bi = 1 means the duty cycle is calculated from the relative width of the logic one. when bi = 0 the duty cycle is calculated from the relative width of the logic zero. bits bz5:bz0 (5:0) define the duty cycle of the pwm squarewave, according to the following formula: duty cycle = cr11(5:0) x 0.78125 %, where cr11 (5:0) is the decimal equivalent of binary value bz5:bz0. control register cr14 (for testing) bits am2:am0 (7:5) control the analog multiplexer. different analog test signals can be fed to test pads. test pads are not wire bonded in production packages. bits dm2:dm0 (4:2) control the digital multiplexer. different test signals can be fed to the tx output pin. bit mux (1) connects the test outputs to the tx output pin. it is for device testing. bit edx (0) enables the tx output continuously. no pull-up resistor is needed when tx pin is the only output for the reading device and edx is written high.
da9090b.001 january 14, 1998 27 application information typical application of mas9090 for digital cellular systems a/d d/a a/d d/a control function memory display keyboard power modem equalizer channel codec speech codec digital baseband mas9090 rf typical application circuit of mas9090 rx lo cclk cs ci co fs mclk tx mic3- mic2- mic1- mic1+ mic2+ mic3+ bz sp1- sp1+ sp1+ sp2- speech codec processor 512 khz 8 khz micro controller vcca vccp vcc gnda gndp gnd 2.7-3.6v (3v mode) or 4.5-5.5v (5v mode) 0v 30 ohm/50 pf + -
da9090b.001 january 14, 1998 28 package outlines and recommended land patterns 0.10 2.35 0.30 2.65 plane seating 18.10 17.70 10.65 pin 1 10.00 7.60 7.40 1.27 typ. 0.33 0.51 0 . 4 0 1 . 2 7 28 lead so outline (300 mil body) all measurements in mm 0.75 x 45 0 - 8 typ. 0.25 0 . 2 3 0 . 3 2 11.68 7.11 0.69 1.27 pcb layout 10.00 typical 12.00 typical 0 - 7 0.80 typical 44 lead tqfp outline all measurements in mm 12.00 typical 10.00 typical 0.75 0.45 0.45 0.30 0.15 0.05 0 . 0 9 0 . 2 0 seating plane 1.45 1.35 max 1.60 14.47 10.53 0.55 0.80 pcb layout 14.47 10.53
da9090b.001 january 14, 1998 29 ordering information product code product package comments mas9090bs low voltage 14-bit linear codec so28 mas9090bs-t low voltage 14-bit linear codec so28 tape and reel mas9090bj low voltage 14-bit linear codec tqfp44 MAS9090BJ-T low voltage 14-bit linear codec tqfp44 tape and reel local distributor micronas contacts micronas semiconductor gmbh lohweg 29 d-85375 neufahrn, germany tel. (08165) 9521 0 tel. int. + 49 8165 9521 0 telefax + 49 8165 9521 99 micronas semiconductor sa ch. chapons-des-prs ch-2022 bevaix, switzerland tel. (032) 847 0111 tel. int. +41 32 847 0111 telefax +41 32 846 1930 micronas oy kamreerintie 2, p.o.box 51 fin-02771 espoo, finland tel. (09) 80521 tel. int. +358 9 80521 telefax +358 9 8053213 notice micronas reserves the right to make changes to the products contained in this data sheet in order to improve the design or perf ormance and to supply the best possible products. micronas assumes no responsibility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights unless otherwise specified in this data sheet, and makes no claim that the circuits ar e free from patent infringement. applications for any devices shown in this data sheet are for illustration only and micronas makes no clai m or warranty that such applications will be suitable for the use specified without further testing or modification.
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